The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure that includes a ferroelectric capacitor that is in series with an underlying functional gate structure and a method of forming the same.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
Recently, negative capacitance ferroelectric finFETs have drawn attention for extending beyond current CMOS technology. Use of ferroelectric materials with negative capacitance such as, for example, HfZrO, in series with the gate stack of a MOSFET can dramatically increase the total capacitance of the MOSFET and can achieve steep threshold voltage swings.
Using existing technology, integration of a ferroelectric capacitor in a replacement gate process flow is challenging due to limited space for device formation and/or shorting of the ferroelectric capacitor. As such, there is a need for providing a method in which a ferroelectric capacitor can be readily integrated in a replacement gate process flow, while circumventing the space issue and/or shorting issue that hampers existing technology.